The present invention is directed towards a method and apparatus for interleaving read and write accesses to a frame buffer.
Digital imaging involves processing digital images to direct the time-dependent switching of an array of pixels in a digital display. In this application, digital imaging is described with respect to digital color displays, but it may be applied to any device that receives digital data and produces a pixelated digital image.
Color displays generate color images by modulating, analyzing, and combining component color bands. Color displays typically use several component colors (such as the primary additive colors, red, green and blue) to generate a multitude of colors for display. A component color band is a portion of the light spectrum corresponding to a component color.
Digital color imaging transfers a digital color image to a digital color pixel display The digital color image is typically separated into three sets of color intensity data corresponding to the three component colors. The three sets of color intensity data are processed through three separate data channels, and recombined at the display.
The color intensity data for each color band is preferably transferred to the display using inexpensive circuitry having limited bandwidth. It is thus advantageous to re-order the color intensity data and store it as a sequence of single-bit arrays of image data (referred to below as bit-planes). The bit-planes are commonly stored in a bit-plane buffer, and then delivered sequentially to frame buffers. Once stored in a frame buffer, the bit-planes are then read out to the display in order to control the display pixels.
Each bit of data in a bit-plane has a specific storage site in a frame buffer and controls a corresponding specific pixel on the display. Thus, a bit-plane can be subdivided into blocks of data that are stored in specified portions of a frame buffer called data banks. These data banks control discrete subdivisions (pixel banks) of the array of pixels in the display.
A data channel of a digital imaging device 100 is illustrated in FIG. 1. As shown in FIG. 1, digital imaging device 100 includes (1) a digital image processor 110; (2) a gamma corrector 120; (3) a bit-plane remapper 130; (4) a bit-plane buffer 140; (5) data select circuitry 150 and 155; (6) frame buffers 160 and 165; (7) memory controllers 170 and 175; and (8) a digital pixel display 180.
The digital image processor 110 receives either a digital input 102, or an analog input 104. Analog input is converted to digital input by an analog to digital (A/D) converter 115 that is connected to or is a part of the digital image processor 110. The digital image processor 110 can perform a number of processing operations on the digital image. For instance, it can perform scaling, frame rate conversion, smoothing, etc. The gamma corrector 120 receives the processed digital image from the digital image processor 110, and adjusts the image intensity data to correct for the data and display type. The gamma corrector 120 can, for example, receive 8-bit, 256 level intensity data from the digital image processor 110 and output adjusted level 10-bit intensity data. The bit-plane remapper 130 converts the gamma-corrected intensity data from a multi-bit single-array format to a format comprising a sequence of bit-planes. For example, the bit-plane remapper 130 can receive an array of 10-bit image intensity data from the gamma corrector 120 and remap it into 10 re-ordered bit-planes. These bit-planes are stored in a bit-plane buffer 140. The bit-plane buffer 140 can, for example, receive 10 re-ordered bit-planes from the bit-plane remapper 130, store them in order, and deliver their data to data select circuitry 150 when requested.
Data select circuitry 150 retrieves data from the bit-plane buffer 140 and stores it in the SDRAM of frame buffers 160 and 165, at locations in the frame buffer specified by addresses generated by the memory controllers 170 and 175. Data select circuitry 155 retrieves data from the locations in the frame buffer specified by the addresses generated by the memory controllers 170 and 175. Data select circuitry 155 commonly retrieves one bit-plane of data from one frame buffer (e.g., Frame Buffer A 160) while data select circuitry 150 is storing another bit-plane of data in the other frame buffer (e.g., Frame Buffer B 165)
At times specified by the memory controllers 170 and 175, data select circuitry 155 selects data from the specified data banks of the active frame buffer and transfers it to corresponding pixel banks of the display 180 to update parts of the image. The light valves of the display 180 are driven by the data retrieved from the frame buffers 160 and 165. The display 180 switches the pixel light valves of a pixel bank on or off as directed by each data set read out from a corresponding data bank of either Frame Buffer A 160 or Frame Buffer B 165.
Data is commonly transferred through Frame Buffer A 160 and Frame Buffer B 165 using the swing buffer approach illustrated in the swing buffer data flow diagram 200 of FIG. 2. As shown in FIG. 2, the swing buffer data flow diagram 200 includes: (1) Frame buffer A 160; (2) Frame buffer B 165; (3) data write processes 211, 212, 213 and 214; (4) data read processes 221, 222, 223 and 224; and (5) a time line 230.
Frame buffers 160 and 165 store bit-plane image data as described in reference to FIG. 1. Data write processes (writes) (e.g., 211-214) comprise transferring data from the bit-plane buffer 140, through data select 150, to a frame buffer (160 or 165). Data read processes (reads) (e.g., 221-224) comprise transferring data from a frame buffer (160 or 165), through data select 155, to the digital pixel display 180. The time line 230 shows the relative time when writes and reads are performed on Frame Buffer A 160 and Frame Buffer B 165.
Under the swing buffer approach 200, one bit-plane is typically read out from a previously filled Frame Buffer A 160, at 221, while a second bit-plane is concurrently written to Frame Buffer B 165, at 212. At the completion of the read and write operations 221 and 212, the roles of Frame Buffer A 160 and Frame Buffer B 165 are reversed. The second bit-plane is then read out from Frame Buffer B 165, at 222, while a third bit-plane is written to Frame Buffer A 160, at 213. By this method, half of the bit-planes of a bit-plane sequence stored in bit-plane buffer 140 are transferred through Frame Buffer A 160, and the other half are transferred through Frame Buffer B 165. For example, the first, third, fifth, seventh and ninth bit-planes of a ten bit-plane image may pass through Frame Buffer A 160 while the second, fourth, sixth, eighth and tenth bit-planes pass through Frame Buffer B 165.
This swing buffer approach to data flow requires two separate frame buffer devices along with appropriate steering logic to route the data. Separate memory controllers are further used to generate the correct addressing and commands for each of the frame buffer SDRAM""s. Unfortunately, this circuitry is relatively complicated and expensive. Other prior known solutions to data flow through a frame buffer tradeoff cost for lower bus speeds that are attainable with programmable logic. These solutions exist in prototype form only.
Therefore, there is a need in the art for a method and apparatus for data flow through a frame buffer that requires less complicated circuitry. This data flow system should (1) require only one frame buffer per data channel; (2) require less interface logic; and (3) reduce the overall cost of a data flow solution for digital imaging.
Some embodiments of the invention comprise digital imaging devices that interleave read and write access to a frame buffer. By interleaving read and write access, a single storage device and less interface logic can be used to transfer bit-planes from a storage device to a display. In a three channel imaging device, this reduces the number of frame buffer SDRAM units from six to three, and significantly reduces the overall cost associated with implementing data flow through the data storage and frame buffer blocks of a digital imaging device.
A data channel having interleaved read and write access to a frame buffer includes (1) a storage device that stores sequences of bit-planes; (2) a frame buffer that stores the re-ordered bit-plane data in groups; (3) a data controller that directs the timing of data writes to and reads from the frame buffer; and (4) a display that turns pixels on and off as directed by received single-bit data.
In some embodiments, the process of transferring data through a single frame buffer by interleaving reads and writes to the frame buffer includes (1) alternately writing to the frame buffer and reading from the frame buffer portions of each bit-plane of a sequence of bit-plane data; and (2) writing to said frame buffer so as to replace each said portion of a bit-plane in the frame buffer with a corresponding portion of a next bit-plane.
In other embodiments, the process of interleaving reads and writes to the single frame buffer includes (1) alternately writing a portion of said data to said frame buffer and reading a portion of said data from said frame buffer; and (2) after reading a first portion of said data from said frame buffer, writing each said a portion of said data so as to replace a portion of said data in said frame buffer that had been previously read from said frame buffer.
In other embodiments, the process of interleaving reads and writes to the single frame buffer includes alternately writing a portion of said data to and reading a portion of said data from said frame buffer, wherein each said reading a portion of said data comprises reading a different portion of data than that written to said frame buffer during the immediately prior said writing a portion of said data.